MJ Logic Design
Full-Feature DMA Controller

This 24 channel, linked-list based DMA block provided four AMBA-AHB Master
interfaces (300 MHz) for implementing DMA transfers between system
memory (SRAM, DRAM) and various high- and low-speed peripherals (e.g.,
Ethernet, PCI/PCI-X, Serial Port, etc).  Separate source and destination
transfer processors and an internal, per-channel transfer buffer supported
independent source and destination transfers that utilized the full AHB bus
bandwidth.  Scatter/gather functionality and both single- and dual-master
(AHB) transfers were also supported.  Key block features included:  
  • per-channel controls that included scatter/gather parameters
  • a descriptor-based control scheme that used linked lists to queue,
    process, and monitor transfers
  • per-channel peripheral interface for synchronizing transfers to
    peripheral operation
  • pre/postfix operations per transfer that allowed the DMA to interact
    autonomously with peripherals w/o per-packet software intervention (e.
    g., on Rx packet EOP, the DMA read the packet length and error status
    from the Ethernet MAC, and stored that information in the resulting
    descriptor chain)
  • programmable interrupts